<div class="content-intro"><p>Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century’s most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril’s family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.</p></div><h2 id="StaffFPGAEngineerWIP-ABOUTTHETEAM">ABOUT THE TEAM</h2> <p>The Battlespace Awareness (BA) team develops state-of-the-art radar systems, deployed to tackle the most significant security challenges of America and its allies. Working across hardware, software, and firmware; in both the RF and digital domains; the team delivers radar architectures that enable advanced surveillance, reconnaissance, and targeting in the contemporary and future battlespace. The Radar team is responsible for all aspects of radar system development; from concepts and architectures through to fielding and sustainment. In this role, you will work closely with an interdisciplinary technical team to define radar architectures, design solutions, build prototypes, perform testing, and mature the prototypes into products.<br> </p> <h2 id="StaffFPGAEngineerWIP-ABOUTTHEJOB">ABOUT THE JOB</h2> <p>We are looking for a Senior FPGA Engineer to join our rapidly growing team in Costa Mesa, CA. In this role, you will be the technical lead for FPGA development supporting our airborne radar products, establishing the foundation for FPGA design processes and best practices. You will be responsible for translating algorithmic requirements into FPGA implementations, leading signal processing design efforts, and collaborating with our Fort Collins team to ensure seamless integration across projects. This will require expertise in FPGA design, signal processing, RTL development (SystemVerilog/VHDL), and Xilinx toolchains. If you are a self-directed technical leader who thrives on establishing new capabilities and can take an algorithm document and independently drive it through to hardware implementation, then this role is for you.<br> </p> <h2 id="StaffFPGAEngineerWIP-WHATYOU'LLDO">WHAT YOU'LL DO</h2> <ul> <li class="text-start" data-uuid="e27e2732-64e9-44ca-a11e-8f7b3c88b3b5">Lead FPGA architecture, design, and verification efforts for airborne radar systems from concept through production</li> <li class="text-start" data-uuid="b70a75f6-9efe-4f36-a50f-59348d478246">Translate signal processing algorithms into efficient, high-performance FPGA implementations on Xilinx SOC/FPGA platforms</li> <li class="text-start" data-uuid="3bc4a7e3-4afa-4956-bfcb-565768542340">Establish and drive robust FPGA design processes, coding standards, and verification methodologies for the airborne products team</li> <li class="text-start" data-uuid="2ce1c7c0-0355-4ab3-acaf-77879147b20b">Collaborate with the Battlespace Awareness engineering team to ensure design consistency and knowledge transfer across sites</li> <li class="text-start" data-uuid="b7c157b1-b122-4c1c-aabc-f124e8a5e5fb">Design and implement digital signal processing chains for radar systems, including data acquisition, filtering, and real-time processing</li> <li class="text-start" data-uuid="f153e491-d581-4579-9ddc-89112254d173">Perform timing analysis, resource optimization, and debugging of complex FPGA designs</li> <li class="text-start" data-uuid="038a9be7-c72f-4c37-9aea-73fc34ac2187">Develop and maintain design documentation, including architecture specifications, design reviews, and verification plans</li> <li class="text-start" data-uuid="da5e9cd0-3e10-46d0-8203-deba1dea76eb">Mentor and guide other engineers as the team scales FPGA capabilities </li> </ul> <h2 id="StaffFPGAEngineerWIP-REQUIREDQUALIFICATIONS">REQUIRED QUALIFICATIONS</h2> <ul> <li data-uuid="c2f40332-52c7-426b-a9ff-4004f54de870">Bachelors degree in electrical engineering, electronics engineering, computer engineering or related field.</li> <li data-uuid="c2f40332-52c7-426b-a9ff-4004f54de870">12+ years of professional experience in FPGA design and development</li> <li class="text-start" data-uuid="92a99285-22a1-40f6-af65-9e6925549f38">Strong expertise in RTL design using SystemVerilog and/or VHDL</li> <li class="text-start" data-uuid="dc6b982b-8292-41bc-bb64-91a48db88aab">Demonstrated experience with Xilinx FPGA devices and development tools (Vivado, Quartus, etc.)</li> <li class="text-start" data-uuid="23349a08-0bd4-4d43-b629-743446326806">Proven experience in digital signal processing implementation on FPGAs</li> <li class="text-start" data-uuid="d344a7c3-b2a5-43e9-8c9a-2a54b7bf1857">Self-directed technical leadership with ability to independently drive projects from requirements to implementation</li> <li class="text-start" data-uuid="66c18cd8-d803-458b-a43e-fb7d4313cbfc">Experience with FPGA verification methodologies and simulation tools</li> <li class="text-start" data-uuid="766b5a6f-fa10-4f89-8982-db6581b94fbf">Strong understanding of timing closure, resource optimization, and FPGA design constraints</li> <li class="text-start" data-uuid="c65b4277-7619-4268-b95e-24e1786ad1af">Eligible to obtain and maintain an active U.S. Secret security clearance </li> </ul> <h2 id="StaffFPGAEngineerWIP-PREFERREDQUALIFICATIONS">PREFERRED QUALIFICATIONS</h2> <ul> <li class="text-start" data-uuid="54ba3ef7-2df9-4355-9487-a0650fa5c15c">Experience with radar systems or software-defined radio development</li> <li class="text-start" data-uuid="53d4e7fd-7979-4303-a8cb-7d579cfd22c3">Familiarity with high-speed interfaces (PCIe, Ethernet, JESD204B, etc.)</li> <li class="text-start" data-uuid="74b0d28a-ff8a-4694-b030-cbb6ef945fba">Experience with Xilinx Zynq UltraScale+, Altera AgileX, or RFSoC platforms</li> <li class="text-start" data-uuid="dbb79570-2e14-42f9-bd0c-36d91610f456">Knowledge of embedded software development for FPGA SoC platforms</li> <li class="text-start" data-uuid="10d246f6-80f5-4ae5-bdd9-432e7ad7bfac">Experience with MATLAB and algorithm-to-hardware workflows</li> <li class="text-start" data-uuid="5c0293c7-1380-4227-9b19-70223beea698">Understanding of RF systems and digital front-end design</li> <li class="text-start" data-uuid="6a508b1b-0507-4efb-a8e2-09de0dd00598">Familiarity with DO-254 or similar hardware design standards for airborne systems</li> <li class="text-start" data-uuid="b573a82d-6ff5-4814-a0dc-01925652255f">Experience with version control (Git) and continuous integration workflows</li> <li class="text-start" data-uuid="152de311-bca0-4cdb-b0ab-a7b05b184436">Background in aerospace or defense systems development</li> </ul> <p> </p><div class="content-pay-transparency"><div class="pay-input"><div class="title">US Salary Range</div><div class="pay-range"><span>$191,000</span><span class="divider">—</span><span>$253,000 USD</span></div></div></div><div class="content-conclusion"><p><span data-contrast="auto">The salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are included in the majority of full time offers; and are considered part of Anduril's total compensation package. Additionally, Anduril offers top-tier benefits for full-time employees, including:</span><span data-ccp-props="{"134233117":false,"134233118":false,"335551550":0,"335551620":0,"335559738":240,"335559739":240}"> </span></p> <p><strong><span data-contrast="auto">Healthcare Benefits </span></strong></p> <ul> <li><strong><span data-contrast="none">US Roles:</span></strong><span data-contrast="none"> Comprehensive medical, dental, and vision plans at little to no cost to you.</span><span data-ccp-props="{"134233117":false,"134233118":false,"335551550":0,"335551620":0,"335559738":0,"335559739":0}"> &lt

Senior FPGA Engineer

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